Currently, some of the fastest digital circuits, particularly those used in multi-Gigabyte/second (multi-Gb/s) data communication systems and test equipment applications, are implemented using current mode logic (hereinafter “CML”). CML requires bias voltages of about 3.3V–5V to provide a satisfactory level of performance.
While very high speed operation in desirable, it is also recognized that circuits operating at higher voltages dissipate greater amounts of power than do circuits operating at lower voltages. In the course of their operation, circuits generate heat that is proportional to their power consumption. This heat needs to be dissipated using a combination of heat sinks, convection, forced air, and liquid cooling. Since power is proportional to the product of voltage and current (P=IV), reducing the power supply voltage, or reducing a reference voltage difference, leads to a corresponding reduction in heat. The heat issue is of particular importance in systems featuring very high circuit density, such as microprocessors and multi-channel communication systems, and has been recognized by the industry as one of the major obstacles for the future advances of the information technology. Additionally, semiconductor technology scaling leads to continued reduction in power supply voltages, and implementing selected high speed circuit components which require high voltages and dedicated power supplies complicates the power distribution problem, and it requires more “real estate” at both the chip and the board level. Accordingly, there is a need for circuits that can attain very high switching speeds, but which offer better power dissipation and reduced size by requiring smaller reference voltage differences, or colloquially, lower voltage of operation (relative to ground).